Summary
Overview
Work History
Education
Skills
Personal Information
Publications
Timeline
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IOANA RADU

Bucharest

Summary

Hardware Verification Engineer with 13 years in the semiconductor industry, of which 9 years focusing on digital and mixed-signal verification of complex ICs. Proficient in System Verilog and UVM methodology, with a background in developing robust testbenches, verification strategies and comprehensive verification plans. Utilizing analytical thinking to identify and resolve verification challenges. Collaborating with cross-functional teams and driving verification process to successful completion.

Overview

15
15
years of professional experience

Work History

Mixed-Signal Verification Consultant

MELEXIS
10.2023 - Current

Pressure/Temperature Sensor with I2C protocol

Motor Drivers with UART, I2C protocols and integrated software control

  • Development of mixed-signal tests and automated checkers in System Verilog and Verilog-AMS with focus on digital and software functionalities
  • Simulation and debugging of more complex top-level systems that integrated analog, digital, and software components, successfully identifying and resolving critical issues to meet project milestones.
  • Comprehensive documentation done for all implemented test cases

Digital Verification Consultant

ERICSSON
03.2019 - 10.2022

Digital Pre-Distorter (DPD) with AXI/APB protocol

  • Development of verification strategies and digital verification plan for sub-system and top level
  • Creation and optimization of UVM-based testbenches including: constraint random functional tests checkers, sequences, coverage, monitors, scoreboards with focus on reusability
  • Simulation and debug of top-level and sub-system tests
  • Running regressions and generating verification reports
  • TLV (Top Level Verification) environment
  • Transferring tests from System Verilog in C language for TLV
  • Running and debugging the DPD in the full system with DAC, ADCs and analog antenna model.

Mixed-Signal Verification Consultant

MELEXIS
05.2018 - 03.2019

Pressure/Temperature Sensor with SENT/UART protocol and software control

  • Development of mixed-signal tests, checkers and AMS models in Verilog-AMS
  • Running and debugging top level simulations (analog, digital and software)
  • Development of fault injection tests, scripts and reports

Verification Consultant

TEXAS INSTRUMENTS
07.2016 - 07.2017

Buck-Boost convertors, Gate driver with I2C protocol

  • Development of mixed-signal tests, checkers, coverage in System Verilog using UVM and in Verilog-AMS
  • Running regressions, generating coverage reports

Verification Engineer

INFINEON TEHNOLOGIES
05.2013 - 06.2016

SBCs (System Basis Chip) with SPI, CAN protocols, Half Bridge Driver with UART protocol

  • Ownership for top level mixed signal verification
  • Development of verification plan and verification environment in Specman and System Verilog using UVM
  • Running and debugging test cases, running regressions, generating coverage reports
  • Ownership for fault injection simulations -Running tests and generating reports using Perl scrips

Junior Analog Designer

INFINEON TEHNOLOGIES
07.2009 - 04.2013

Multiple Half Bridge Drivers

  • Scaling of entire chip, from a higher number of bridges to a smaller number
  • Block level and top level simulations, redesign of current limitation and low side driver

Education

Master's degree - Advanced Microelectronics

University "Politehnica" of Bucharest
07.2012

Bachelor's degree - Microelectronics

University "Politehnica" of Bucharest
07.2010

Mathematics and Informatics

"Tudor Vianu" National College
06.2006

Skills

  • System Verilog
  • UVM
  • Verification Plan
  • Verification Strategy
  • RTL/Mixed Signal Simulation and Debug
  • Functional and Code Coverage
  • Vmanager, Vplan
  • Assertion-Based Verification
  • C, C
  • ClearCase, Desing Sync
  • JIRA
  • Verilog AMS

Personal Information

  • Title: VERIFICATION ENGINEER
  • Date of Birth: 07/10/87

Publications

  • Semiconductor Conference (CAS) “Constraint random stimuli and functional coverage on mixed signal verification", 2014
  • Semiconductor Conference (CAS) "Power limitation protection function in integrated low side switches", 2013

Timeline

Mixed-Signal Verification Consultant

MELEXIS
10.2023 - Current

Digital Verification Consultant

ERICSSON
03.2019 - 10.2022

Mixed-Signal Verification Consultant

MELEXIS
05.2018 - 03.2019

Verification Consultant

TEXAS INSTRUMENTS
07.2016 - 07.2017

Verification Engineer

INFINEON TEHNOLOGIES
05.2013 - 06.2016

Junior Analog Designer

INFINEON TEHNOLOGIES
07.2009 - 04.2013

Master's degree - Advanced Microelectronics

University "Politehnica" of Bucharest

Bachelor's degree - Microelectronics

University "Politehnica" of Bucharest

Mathematics and Informatics

"Tudor Vianu" National College
IOANA RADU