Mihaela Maiorescu Scanteianu
Iaşi,Iasi
Summary
Professional with 10+ expertise in E (Specman), e-UVM, Git, C/C++, System Verilog, Matlab & Simulink.
Problem-solving team player with experience identifying root causes of engineering faults. Creates thorough policies and procedures for quality assurance and best practices.
Overview
17
17
years of professional experience
6
6
years of post-secondary education
Work history
ASIC Verification Engineer
INTEL
Iasi, Iasi
2022.08 - Current
- Executed verification of Wifi PHY layer protocol across TX/RX functional and system flows.
- Refined testing environments by optimising coverage and enabling upper-layer support.
- Established advanced debug functionalities to boost efficiency of system flow.
- Leda team of 4 ASIC engineers as block owner since last year.
ASIC Verification Engineer
Nobug Consulting
Iasi, Romania
2012.01 - 2022.08
- Responsible with the verification of Wifi PHY layer protocol on the following areas: functional (TX/RX), system flows (new debug capabilities and system flows), coverage optimization, FC support, part of DSP AV team.
- Tools/Languages: Specman/e, NCSim, Xcelium
Network Engineer
E.ON IT ROMANIA
Iasi
2008.09 - 2012.03
- 2nd level user support insurance, Order /Incident /KPI Management.
Education
Erasmus stage - digital design/embedded systems
Ecole Nationale Supérieure De L'Electronique Et De Ses Applications
2012.03 - 2012.08
M.Sc. - Modern Signal Processing Techniques
Technical University Gheorghe Asachi
Iasi 2010.09 - 2012.09
Bachelor of Science - Microelectronics, Optoelectronics and Nanotechnologies
Technical University Gheorghe Asachi
Iasi 2006.09 - 2010.09
Skills
- Git
- E (Specman)
- UVM
- C/C
- System verilog
- Matlab & Simulink
- Communication skills
- Customer-Focused approach
- Data interpretation and analysis
- Solution engineering
Languages
English
Proficient (C2)
French
Elementary
Trainings
- Nobug Consulting, 08/01/13, 09/01/13, Cadence Training UVM - System Verilog, SimVision, SV
- 03/01/13, 07/01/13, Cadence Training UVM on Specman, Specman, NCSim, e
- 11/01/12, 02/01/13, Block level verification of RBC, Specman eRM training project, Specman 6.2 (e), NcVerilog
Timeline
ASIC Verification Engineer
INTEL
2022.08 - Current
Erasmus stage - digital design/embedded systems
Ecole Nationale Supérieure De L'Electronique Et De Ses Applications
2012.03 - 2012.08
ASIC Verification Engineer
Nobug Consulting
2012.01 - 2022.08
M.Sc. - Modern Signal Processing Techniques
Technical University Gheorghe Asachi
2010.09 - 2012.09
Network Engineer
E.ON IT ROMANIA
2008.09 - 2012.03
Bachelor of Science - Microelectronics, Optoelectronics and Nanotechnologies
Technical University Gheorghe Asachi
2006.09 - 2010.09