Mihaela Maiorescu Scanteianu
Iaşi,Iasi
Summary
Professional with 10+ expertise in E (Specman), e-UVM, Git, C/C++, System Verilog, Matlab & Simulink.
Problem-solving team player with experience identifying root causes of engineering faults. Creates thorough policies and procedures for quality assurance and best practices.
Overview
17
17
years of professional experience
6
6
years of post-secondary education
Work history
ASIC Verification Engineer
INTEL
Iasi, Iasi
08.2022 - Current
- Executed verification of Wifi PHY layer protocol across TX/RX functional and system flows.
- Refined testing environments by optimising coverage and enabling upper-layer support.
- Established advanced debug functionalities to boost efficiency of system flow.
- Leda team of 4 ASIC engineers as block owner since last year.
ASIC Verification Engineer
Nobug Consulting
Iasi, Romania
01.2012 - 08.2022
- Responsible with the verification of Wifi PHY layer protocol on the following areas: functional (TX/RX), system flows (new debug capabilities and system flows), coverage optimization, FC support, part of DSP AV team.
- Tools/Languages: Specman/e, NCSim, Xcelium
Network Engineer
E.ON IT ROMANIA
Iasi
09.2008 - 03.2012
- 2nd level user support insurance, Order /Incident /KPI Management.
Education
Erasmus stage - digital design/embedded systems
Ecole Nationale Supérieure De L'Electronique Et De Ses Applications
03.2012 - 08.2012
M.Sc. - Modern Signal Processing Techniques
Technical University Gheorghe Asachi
Iasi 09.2010 - 09.2012
Bachelor of Science - Microelectronics, Optoelectronics and Nanotechnologies
Technical University Gheorghe Asachi
Iasi 09.2006 - 09.2010
Skills
- Git
- E (Specman)
- UVM
- C/C
- System verilog
- Matlab & Simulink
- Communication skills
- Customer-Focused approach
- Data interpretation and analysis
- Solution engineering
Languages
English
Proficient (C2)
French
Elementary
Trainings
- Nobug Consulting, 08/01/13, 09/01/13, Cadence Training UVM - System Verilog, SimVision, SV
- 03/01/13, 07/01/13, Cadence Training UVM on Specman, Specman, NCSim, e
- 11/01/12, 02/01/13, Block level verification of RBC, Specman eRM training project, Specman 6.2 (e), NcVerilog
Timeline
ASIC Verification Engineer
INTEL
08.2022 - Current
Erasmus stage - digital design/embedded systems
Ecole Nationale Supérieure De L'Electronique Et De Ses Applications
03.2012 - 08.2012
ASIC Verification Engineer
Nobug Consulting
01.2012 - 08.2022
M.Sc. - Modern Signal Processing Techniques
Technical University Gheorghe Asachi
09.2010 - 09.2012
Network Engineer
E.ON IT ROMANIA
09.2008 - 03.2012
Bachelor of Science - Microelectronics, Optoelectronics and Nanotechnologies
Technical University Gheorghe Asachi
09.2006 - 09.2010
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