Mohamed Khalil LAHMAR
Grenoble,France
Summary
Specialized in Siemens EDA tool Tessent, effectively applying its features for both basic and advanced functionalities. Proven expertise in automation and agentic AI, with a solid track record in enablement processes across multinational settings. Committed to enhancing test methodologies, including design, ATPG, and yield improvement strategies.
Overview
3
3
Languages
2
2
years of post-secondary education
4
4
years of professional experience
Work history
Strategic DFT (Senior) CAD Engineer
Onsemi
2026.06 - Current
- Owned DFT insertion automation at RTL and post-synthesis, guiding ATPG participation to streamline testing efforts.
- Executed mapped solutions and automated flows, ensuring alignment across the organisation to improve DFT processes.
- Enabled DFT post-silicon methodologies, establishing business case and project roadmap to enhance design reliability.
Associate Application Engineer
Siemens EDA
Meylan, France
2024.07 - 2025.10
- Completed extensive training in UVM, gaining proficiency in testbench for AXI4 Lite to APB4 bridge design.
- Completed Tessent Scan and ATPG trainings, applying knowledge in both Hierarchical and Flat flows, and inserting Boundary Scan, MBIST, TPSP, OCC, EDT, LBIST and scan cells.
- Investigated features of IJTAG network (IEEE1687), contributing to development of effective testing strategies.
- Developed understanding of fault models to enhance testing processes.
- Experienced Aprisa tool usage and implementation: Floorplanning and power planning, Placement, CTS, and routing.
- Learned SVRF and Followed DRC, and LVS training.
- Acquired Knowledge of rule file optimization and DFM properties.
Digital IC designer Consultant
Elsys Design and Atos Eviden
Sophia Antipolis, France
2024.05 - 2024.06
- Digital IC design of DMA Controller Block for High Performance Computing (HPC) Applications
- Wrote RTL code for the different modules of the Block in SystemVerilog using some design IPs.
- Executed simulations on QuestaSim Visualizer and conducted SpyGlass Lint checks to verify design integrity and compliance with standards.
- Defined Block architecture and drew Block diagrams connecting design IPs and defining FSM.
- Reviewed design specifications (HAS) and defined block specifications (MAS) using Polarion ALM tool to ensure alignment with project requirements.
Associate R&D engineer
CSEM SA
Neuchâtel, Switzerland
2023.03 - 2023.11
- Automate optical inspection of chips to raise inspection throughput significantly - Avoidance of manual load/unload of samples.
- Optimise microlens designs using empirical models and theoretical model exploration.
- Develop microlens processes for quantum sensing and space applications.
Education
Engineering degree - Master degree of Nanotechnologies for ICTs
INPG Phelma jointly with EPFL and Politecnico di Torino
France, Italy and Switzerland 2021.01 - 2023.01
Skills
- DFT Methodologies
- Agentic AI
- Hardware description languages
- Linux, TCL scripts, MakeFile
LANGUAGES
English Fluent
Beginner
French Fluent
Beginner
Arabic Mother tongue
Beginner
Timeline
Strategic DFT (Senior) CAD Engineer
Onsemi
2026.06 - Current
Associate Application Engineer
Siemens EDA
2024.07 - 2025.10
Digital IC designer Consultant
Elsys Design and Atos Eviden
2024.05 - 2024.06
Associate R&D engineer
CSEM SA
2023.03 - 2023.11
Engineering degree - Master degree of Nanotechnologies for ICTs
INPG Phelma jointly with EPFL and Politecnico di Torino
2021.01 - 2023.01